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hyb25dc512800d[e/f] hyb25dc512160d[e/f] hyi25dc512800d[e/f] hyi25dc512160d[e/f](l) 512-mbit double-data-rate sdram ddr sdram eu rohs compliant products internet data sheet rev. 1.10 may 2008
internet data sheet hy[b/i]25dc512[80/16]0d[e/f](l) 512-mbit double-data-rate sdram qag_techdoc_a4, 4.20, 2008-01-25 2 06212007-08mw-k87l we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com revision history: rev. 1.10, 2008-05 adapted internet edition added product hyi25dc512160del-5 25 corrected ioh to -16.2, iol to 16.2 in chapter 5.1 previous revision: rev. 1.00, 2008-03 added new idd values previous revision: rev. 0.60, 2007-11 added new idd values hy[b/i]25dc512[80/16]0d[e/f](l) 512-mbit double-data-rate sdram internet data sheet rev. 1.10, 2008-05 3 06212007-08mw-k87l 1overview this chapter gives an overview of the 512-mbit doub le-data-rate sdram product family and describes its main characteristics. 1.1 features ? double data rate architecture: tw o data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? programmable cas latency: 2, 2.5, 3 and 4 ? programmable burst lengths: 2, 4, or 8 ? programmable drive strength: normal, weak ? auto precharge option for each burst access ? auto refresh and self refresh modes ? ras-lockout supported t rap = t rcd ?7.8 s maximum average periodic refresh interval ? 2.5 v (sstl_2 compatible) i/o ? v dd = 2.5 v 0.2 v, v dd = 2.6 v 0.1 v (ddr500) ? v ddq = 2.5 v 0.2 v, v ddq = 2.6 v 0.1 v (ddr500) ? packages: pg-tsopii-66, pg-tfbga-60 ? rohs compliant products 1) table 1 performance 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polyb rominated biphenyl ethers. for more information please visit www.qimonda.com/green_products . part number speed code ?4 ?5a ?5 ?6 unit speed grade ddr500b ddr400a ddr400b ddr333b ? max. clock frequency @cl4 f ck4 250 200 200 166 mhz @cl3 f ck3 250 200 200 166 mhz @cl2.5 f ck2.5 200 200 166 166 mhz @cl2 f ck2 133 133 133 133 mhz hy[b/i]25dc512[80/16]0d[e/f](l) 512-mbit double-data-rate sdram internet data sheet rev. 1.10, 2008-05 4 06212007-08mw-k87l 1.2 description the 512-mbit double-data-rate sdram is a high-speed cmos, dynamic random-access memory containing 536, 870, 912 bits. it is internally configured as a quad-bank dram. the 512-mbit double-data-rate sdram uses a double- data-rate architecture to ac hieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512-mbit double-data-rate sdram effectively consists of a singl e 2n-bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-ha lf-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (d qs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller dur ing writes. dqs is edge-aligned with data for reads and center-a ligned with data for writes. the 512-mbit double-data-rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipel ined, multibank architecture of ddr sdrams allows for co ncurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all inputs are compatible with the industry standard for sstl_2. all out puts are sstl_2, class ii compatible. note: the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. table 2 ordering information for rohs compliant products product type 1) org. speed cas-rcd-rp latencies 2)3)4) clock (mhz) package note 5) standard temperature range (0 c - 70 c) ddr500b( 3-3-3 ) hyb25dc512160de-4 16 ddr500b 3-3-3 250 pg-tsopii-66 hyb25dc512160df-4 16 ddr500b 3-3-3 250 pg-tfbga-60 hyb25dc512800de-4 8 ddr500b 3-3-3 250 pg-tsopii-66 hyb25dc512800df-4 8 ddr500b 3-3-3 250 pg-tfbga-60 ddr400b( 3-3-3 ) hyb25dc512160de-5 16 ddr400b 3-3-3 200 pg-tsopii-66 hyb25dc512160df-5 16 ddr400b 3-3-3 200 pg-tfbga-60 hyb25dc512800de-5 8 ddr400b 3-3-3 200 pg-tsopii-66 hyb25dc512800df-5 8 ddr400b 3-3-3 200 pg-tfbga-60 ddr400a( 2.5-3-3 ) hyb25dc512160de-5a 16 ddr400a 2.5-3-3 200 pg-tsopii-66 hy[b/i]25dc512[80/16]0d[e/f](l) 512-mbit double-data-rate sdram internet data sheet rev. 1.10, 2008-05 5 06212007-08mw-k87l note: please check with your qimonda representative that leadti me and availability of your preferred device type and version meet your project requirements. hyb25dc512160df-5a 16 ddr400a 2.5-3-3 200 pg-tfbga-60 hyb25dc512800de-5a 8 ddr400a 2.5-3-3 200 pg-tsopii-66 hyb25dc512800df-5a 8 ddr400a 2.5-3-3 200 pg-tfbga-60 ddr333b( 2.5-3-3 ) hyb25dc512160de-6 16 ddr333b 2.5-3-3 166 pg-tsopii-66 hyb25dc512160df-6 16 ddr333b 2.5-3-3 166 pg-tfbga-60 hyb25dc512800de-6 8 ddr333b 2.5-3-3 166 pg-tsopii-66 hyb25dc512800df-6 8 ddr333b 2.5-3-3 166 pg-tfbga-60 industrial temperature range (--40 c - 85 c) ddr500b( 3-3-3 ) hyi25dc512160de-4 16 ddr500b 3-3-3 250 pg-tsopii-66 hyi25dc512160df-4 16 ddr500b 3-3-3 250 pg-tfbga-60 hyi25dc512800de-4 8 ddr500b 3-3-3 250 pg-tsopii-66 hyi25dc512800df-4 8 ddr500b 3-3-3 250 pg-tfbga-60 ddr400b( 3-3-3 ) hyi25dc512160del-5 16 ddr400b 3-3-3 200 pg-tsopii-66 hyi25dc512160de-5 16 ddr400b 3-3-3 200 pg-tsopii-66 hyi25dc512160df-5 16 ddr400b 3-3-3 200 pg-tfbga-60 hyi25dc512800de-5 8 ddr400b 3-3-3 200 pg-tsopii-66 hyi25dc512800df-5 8 ddr400b 3-3-3 200 pg-tfbga-60 ddr400a( 2.5-3-3 ) hyi25dc512800df-5a 8 ddr400a 2.5-3-3 200 pg-tfbga-60 hyi25dc512160de-5a 16 ddr400a 2.5-3-3 200 pg-tsopii-66 hyi25dc512160df-5a 16 ddr400a 2.5-3-3 200 pg-tfbga-60 hyi25dc512800de-5a 8 ddr400a 2.5-3-3 200 pg-tsopii-66 ddr333b( 2.5-3-3 ) hyi25dc512160de-6 16 ddr333b 2.5-3-3 166 pg-tsopii-66 HYI25DC512160DF-6 16 ddr333b 2.5-3-3 166 pg-tfbga-60 hyi25dc512800de-6 8 ddr333b 2.5-3-3 166 pg-tsopii-66 hyi25dc512800df-6 8 ddr333b 2.5-3-3 166 pg-tfbga-60 1) for detailed information regarding product type of qimonda pl ease see chapter "product nomenc lature" of this data sheet. 2) cas: column address strobe 3) rcd: row column delay 4) rp: row precharge 5) rohs compliant product: restriction of the use of certain hazardous substances (r ohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, pol ybrominated biphenyls and polybro minated biphenyl ethers. for more information please vi sit www.qimonda.com/green_products . product type 1) org. speed cas-rcd-rp latencies 2)3)4) clock (mhz) package note 5) hy[b/i]25dc512[80/16]0d[e/f](l) 512-mbit double-data-rate sdram internet data sheet rev. 1.10, 2008-05 6 06212007-08mw-k87l 2 configuration this chapter contains the chip configuration and block diagrams. 2.1 configuration for tfbga-60 the ball configuration of a ddr s dram is listed by function in table 3 . the abbreviations used in the ball#/buffer type column are explained in table 4 and table 5 respectively. table 3 configuration ball# name pin type buffer type function clock signals g2 ck1 i sstl clock signal g3 ck1 i sstl complementary clock signal h3 cke i sstl clock enable control signals h7 ras i sstl row address strobe g8 cas i sstl column address strobe g7 we i sstl write enable h8 cs i sstl chip select address signals j8 ba0 i sstl bank address bus j7 ba1 i sstl k7 a0 i sstl address bus l8 a1 i sstl l7 a2 i sstl m8 a3 i sstl m2 a4 i sstl l3 a5 i sstl l2 a6 i sstl k3 a7 i sstl k2 a8 i sstl j3 a9 i sstl k8 a10 i sstl ap i sstl j2 a11 i sstl h2 a12 i sstl hy[b/i]25dc512[80/16]0d[e/f](l) 512-mbit double-data-rate sdram internet data sheet rev. 1.10, 2008-05 7 06212007-08mw-k87l data signals 8 organization a8 dq0 i/o sstl data signal bus 7:0 b7 dq1 i/o sstl c7 dq2 i/o sstl d7 dq3 i/o sstl d3 dq4 i/o sstl c3 dq5 i/o sstl b3 dq6 i/o sstl a2 dq7 i/o sstl data strobe 8 organization e3 dqs i/o sstl data strobe data mask 8 organization f3 dm i sstl data mask data signals 16 organization a8 dq0 i/o sstl data signal 15:0 b9 dq1 i/o sstl b7 dq2 i/o sstl c9 dq3 i/o sstl c7 dq4 i/o sstl d9 dq5 i/o sstl d7 dq6 i/o sstl e9 dq7 i/o sstl e1 dq8 i/o sstl d3 dq9 i/o sstl d1 dq10 i/o sstl c3 dq11 i/o sstl c1 dq12 i/o sstl b3 dq13 i/o sstl b1 dq14 i/o sstl a2 dq15 i/o sstl data strobe 16 organization e3 udqs i/o sstl data strobe upper byte e7 ldqs i/o sstl data strobe lower byte data mask 16 organization f3 udm i sstl data mask upper byte f7 ldm i sstl data mask lower byte power supplies f1 v ref ai ? i/o reference voltage a9, b2, c8, d2, e8 v ddq pwr ? i/o driver power supply ball# name pin type buffer type function hy[b/i]25dc512[80/16]0d[e/f](l) 512-mbit double-data-rate sdram internet data sheet rev. 1.10, 2008-05 8 06212007-08mw-k87l table 4 abbreviations for ball type table 5 abbreviations for buffer type a7, f8, m7 v dd pwr ? power supply a1, b8, c2, d8, e2 v ssq pwr ? power supply a3, f2, m3 v ss pwr ? power supply not connected 8 organization b1, b9, c1, c9, d1, d9, e1, e7, e9, f7, f9 nc nc ? not connected not connected 16 organization f9 nc nc ? not connected abbreviation description i standard input-only pin. digital levels o output. digital levels i/o i/o is a bidirectional input/output signal ai input. analog levels pwr power gnd ground nc not connected abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 ope rational states, active low and tristate, and allows multiple devices to share as a wire-or ball# name pin type buffer type function hy[b/i]25dc512[80/16]0d[e/f](l) 512-mbit double-data-rate sdram internet data sheet rev. 1.10, 2008-05 9 06212007-08mw-k87l figure 1 configuration for x8 orga nization, tfbga-60, top view 0 3 3 ' & |